Semiconductor integrated circuit and fabrication method thereof

ABSTRACT

A semiconductor integrated circuit having a high withstand voltage TFT and a TFT which is capable of operating at high speed in a circuit of thin film transistors (TFT) and methods for fabricating such circuit will be provided. A gate insulating film of the TFT required to operate at high speed (e.g., TFT used for a logic circuit) is relatively thinned less than a gate insulating film of the TFT which is required to have high withstand voltage (e.g., TFT used for switching high voltage signals).

BACKGROUND OF THE INVENTION

[0001] The present invention relates to a semiconductor integratedcircuit having a plurality of thin film transistors (TFT) and moreparticularly to a monolithic active matrix circuit having an activematrix circuit and a logic circuit (called also as a peripheral circuit)for driving it on one and the same substrate and to a fabrication methodthereof. The semiconductor integrated circuit fabricated by the presentinvention may be formed either on an insulating substrate such as glassand on an insulating coating film formed on a semiconductor substratesuch as monocrystal silicon for example. The present invention exhibitsits effect specifically in a semiconductor integrated circuit having alarge matrix which operates at low speed and a logic circuit for drivingit which is required to operate at high speed, such as a liquid crystaldisplay.

DESCRIPTION OF RELATED ART

[0002] Recently, researches on an insulated gate type semiconductordevice having a thin film semiconductor layer (also called as an activelayer) on an insulating substrate are being conducted and specifically,researches on a thin film insulated gate transistor, i.e. a so-calledthin film transistor (TFT), are being actively conducted. They arecategorized as an amorphous silicon TFT or a crystal silicon TFTdepending on a material and a crystal state of the semiconductor to beused.

[0003] Generally, a semiconductor in the amorphous state has a smallfield mobility, so it cannot be utilized for a TFT which is required tooperate at high speed. Then, research and development on the crystalsilicon TFT are being conducted in order to fabricate a higherperformance circuit in these days.

[0004] In those TFTs, a thin film semiconductor region of eachindividual thin film transistor is isolated and hence, the channelportion has not been grounded like the conventional semiconductorintegrated circuit on a semiconductor chip. Due to that, deteriorationor failure peculiar to the TFT have occurred sometimes. For instance,with regard to a hot carrier implantation phenomenon, it has beenextremely difficult to remove accumulated charge because the channel hasbeen put in the state of floating potential.

[0005] Then, a gate insulating film has been thickened or appliedvoltage has been reduced in order to prevent the deterioration and thelike caused by the implantation of carrier. However, operating speeddecreases if the gate insulating film is thickened. It has been alsodifficult to reduce the applied voltage because of the requirement of adevice. Because driving voltage of a matrix circuit is determineddepending on a liquid crystal material in the monolithic active matrixcircuit used for a liquid crystal display in particular, it is difficultto change it arbitrarily.

[0006] However, the operating speed of the logic circuit decreases ifthe gate insulating film is thickened. Then, driving voltage has to beincreased to maintain the operating speed, increasing power consumption.

[0007]FIG. 11A is a block diagram showing the monolithic active matrixcircuit used for a liquid crystal display. In the figure, a columndriver 1 and a row driver 2 are provided on a substrate 7 as peripheraldriver circuits, pixel circuits (pixels) 4 each comprising a transistorand a capacitor are formed in a matrix area 3 and the matrix area isconnected with the peripheral circuits through wires 5 and 6.

[0008] Among the TFTs used for the driver circuits, high operating speedis required to the TFT composing the logic circuit such as a shiftregister and high withstand voltage is required to the TFT used in thepixel circuit. Even in the driver circuits, a part of transistors in aswitching circuit (e.g. buffer circuit) is required to have highwithstand voltage, rather than high operating speed.

[0009] Because the high operating speed and the high withstand voltageare contradictory requirements as described above, it has been difficultto form those transistors on one and the same substrate in one and thesame process especially when it is required to reduce the powerconsumption. Accordingly, it is an object of the present invention tosolve such difficult problems.

SUMMARY OF THE INVENTION

[0010] The present invention is characterized in that a thickness of agate insulating film in a circuit in which priority is given to highoperating speed is changed from that of a gate insulating film in acircuit in which priority is given to high withstand voltage. That is,the former is made to be a circuit which is driven in low voltage andoperates at high speed and the latter is made to be a circuit havinghigh withstand voltage by reducing the thickness of the gate insulatingfilm of the former as compared to that of the latter.

[0011] In this case, among peripheral circuits, the circuits in whichpriority is given to high operating speed include logic circuits such asa shift register, a CPU, a memory circuit and a decoder circuit.Further, among peripheral circuits, the circuits in which priority isgiven to high withstand voltage include a high withstand voltageswitching circuit, a buffer circuit and others.

[0012] A matrix circuit is also the circuit in which priority is givento high withstand voltage, though it is not the peripheral circuit.

[0013] Their difference is distinguished by a variation of voltageapplied to the gate electrode in general. That is, the width ofvariation of voltage applied to the gate electrode is small in theformer rather than in the latter.

[0014] Then, a semiconductor integrated circuit of a first invention ischaracterized in that a thickness of at least one gate insulating filmof the thin film transistor of the circuit in which priority is given tohigh operating speed is 80% or less of a thickness of a gate insulatingfilm of the thin film transistor of the circuit in which priority isgiven to high withstand voltage.

[0015] A semiconductor integrated circuit of a second invention ischaracterized in that at least one layer of another insulating layer isused for at least one gate insulating film of the thin film transistorof the circuit in which priority is given to high withstand voltage inaddition to an insulating layer composing at least one gate insulatingfilm of the thin film transistor of the circuit in which priority isgiven to high operating speed.

[0016] A semiconductor integrated circuit of a third invention ischaracterized in that when at least one gate insulating film of the thinfilm transistor of the circuit in which priority is given to highoperating speed is assumed to be a first insulating layer, at least onegate insulating film of the thin film transistor of the circuit in whichpriority is given to high withstand voltage is composed of, in additionto the first insulating layer, a second insulating layer formed in adifferent process from the first insulating layer.

[0017] A semiconductor integrated circuit of a fourth invention ischaracterized in that in the semiconductor integrated circuit having afirst thin film transistor and a second thin film transistor each havinga gate insulating film whose thickness is different, the thickness ofthe gate insulating film of the first thin film transistor is 80% orless of the thickness of the gate insulating film of the second thinfilm transistor and a length of a channel of the first thin filmtransistor is 80% or less of a length of a channel of the second thinfilm transistor.

[0018] The semiconductor integrated circuit of the fourth invention isalso characterized in that the thin film transistor used in theperipheral circuit which is required to operate at high speed ismicronized in accordance to scaling law.

[0019] Specifically, the present invention is characterized in that thelength of the channel in the circuit in which priority is given to highoperating speed is changed from that of the channel in the circuit inwhich priority is given to high withstand voltage. That is, the lengthof the channel of the former is shortened as compared to that of thelatter, or the length of the channel of the latter is prolonged ascompared to that of the former, so as to make the former a transistorwhich is driven in low voltage and which operates at high speed and thelatter a transistor of high withstand voltage.

[0020] Here, the scaling law to reduce physical dimensions of the TFT orwiring composing it, an interlayer film and others in inverselyproportional to a certain coefficient. It allows enhancement ofperformance to be achieved in the same time with highly densifiedseparation of devices.

[0021] According to the present invention, electrical characteristics ofthe peripheral circuit which is required to operate at high speed isimproved by micronizing the channel length and the thickness of the gateinsulating film in particular.

[0022] The micronization of the channel length may be achieved bymodifying a shape of a mask in forming the gate electrode.

[0023] In the first through fourth invention described above, it ispossible to include a low concentration impurity region that is formedby utilizing a difference of the thickness of the gate insulating filmsin the thin film transistor of the circuit in which priority is given tohigh withstand voltage. It allows high withstand voltage characteristicsto be enhanced further.

[0024] Further, in the third invention described above, the chemicalcomposition of the first insulating layer may be differentiated fromthat of the second insulating layer. Thereby, it becomes advantageous infabricating them.

[0025] Similarly to that, in the third invention described above, onlyeither one of the first insulating layer or the second insulating layermay be formed by means of thermal oxidation. It is of course possible toform the both by means of the thermal oxidation.

[0026] As for a method for fabricating the inventive semiconductorintegrated circuit, there are the following inventions. The fifthinvention comprises steps of:

[0027] 1) forming a thin film semiconductor region utilized for a thinfilm transistor of a circuit in which priority is given to highwithstand voltage and a thin film semiconductor region utilized for athin film transistor of a circuit in which priority is given to highoperating speed;

[0028] 2) forming a first insulating layer covering both of the thinfilm semiconductor regions;

[0029] 3) selectively removing the first insulating layer to remove allthe first insulating layer covering the thin film semiconductor regioncomposing at least one of the thin film transistor of the circuit inwhich priority is given to high operating speed by; and

[0030] 4) forming a second insulating layer covering both of the thinfilm semiconductor regions.

[0031] The sixth invention comprises steps of:

[0032] 1) forming a thin film semiconductor region utilized for a thinfilm transistor of a circuit in which priority is given to highwithstand voltage and a thin film semiconductor region utilized for athin film transistor of a circuit in which priority is given to highoperating speed;

[0033] 2) forming a first insulating layer covering both of the thinfilm semiconductor regions;

[0034] 3) forming a second insulating layer covering the firstinsulating layer; and

[0035] 4) selectively removing the second insulating layer to remove allthe first insulating layer covering the thin film semiconductor regioncomposing at least one of the thin film transistor of the circuit inwhich priority is given to high operating speed.

[0036] The seventh invention comprises steps of:

[0037] 1) forming a thin film semiconductor region utilized for a thinfilm transistor of a circuit in which priority is given to highwithstand voltage and a thin film semiconductor region utilized for athin film transistor of a circuit in which priority is given to highoperating speed;

[0038] 2) selectively forming a first insulating layer covering both ofthe thin film semiconductor region except part of the thin filmsemiconductor region composing at least one of the thin film transistorsof at least the circuit in which priority is given to high operatingspeed; and

[0039] 3) forming a second insulating layer covering both of the thinfilm semiconductor regions.

[0040] In the fifth through seventh inventions described above, thefirst insulating layer may be formed by means of thermal oxidation. Thesecond insulating layer may be also formed by means of thermal oxidationas a matter of course.

[0041] The fifth through seventh inventions described above may furthercomprise a step of forming gate electrodes whose width is differentowing to shapes of mask of the gate electrodes so that the width of thegate electrode of the second thin film transistor is larger than thewidth of the gate electrode of the first thin film transistor.

[0042] It also comprises a step of forming a channel region havingalmost the same width with the width of the gate electrode under thegate electrode in a step of doping to the active layer.

[0043] While the length of the channel of the first thin film transistorhas been set to be 80% or less of the length of the channel of thesecond thin film transistor, it has been found that the electricalcharacteristics such as operating speed improves when the ratio of thelength of the channel of the first thin film transistor to that of thesecond thin film transistor is set preferably at 0.1 to 0.5.

[0044] Therefore, the ratio of the width of the gate electrode of thefirst thin film transistor to the width of the gate electrode of thesecond thin film transistor has been set within a range of 0.1 to 0.5.

[0045] The electrical characteristics such as operating speed improvesfurther when the thickness of the gate insulating film of the first thinfilm transistor and the second thin film transistor is adjusted inaccordance to this ratio.

[0046] Thereby, the thickness of the gate insulating film or the channellength may be changed in the circuit which is required to operate athigh speed (e.g. a logic circuit in a monolithic active matrix circuit)and the circuit which is required to have high withstand voltage (amatrix circuit in the monolithic active matrix circuit). As a result, asfor the monolithic active matrix circuit, the logic circuit which isdriven in low voltage and operates at high speed and the high withstandvoltage matrix circuit may be obtained on one and the same substrate,which is the purpose of the present invention. It is noted that asdisclosed in, for example, Japanese Patent Laid Open No. Hei. 7-135323,the disclosure of which is herein incorporated by reference, the presentinvention is applicable to a semiconductor integrated circuit in whichvarious memories and arithmetic devices are provided as logic circuitson one and the same substrate (see FIG. 11B). In FIG. 11B, a correctionmemory 8, a memory 9, an input port 10, a CPU 11, and an XY branch 12are formed on a substrate 7 as well as a column decoder/driver 1, a rowdecoder/driver 2, and an active matrix 3. The present invention will beexplained below in detail with reference to preferred embodiments.

BRIEF DESCRIPTION OF DRAWINGS

[0047]FIGS. 1A through 1F are section views showing a fabricationprocess according to a first embodiment:

[0048]FIGS. 2A through 2F are section views showing a fabricationprocess according to a second embodiment:

[0049]FIGS. 3A through 3F are section views showing a fabricationprocess according to a third embodiment:

[0050]FIGS. 4A through 4F are section views showing a fabricationprocess according to a fourth embodiment:

[0051]FIGS. 5A through 5F are section views showing a fabricationprocess according to a fifth embodiment:

[0052]FIGS. 6A through 6F are section views showing a fabricationprocess according to a sixth embodiment:

[0053]FIGS. 7A through 7C are section views showing a fabricationprocess according to an eighth embodiment:

[0054]FIGS. 8A through 8C are section views showing a fabricationprocess according to a ninth embodiment:

[0055]FIGS. 9A through 9C are section views of the fabrication processof the fifth embodiment using a resist film to selectively obtain athermal oxide film;

[0056]FIGS. 10A through 10C are section views of the fabrication processof the sixth embodiment using a resist film to selectively obtain athermal oxide film;

[0057]FIGS. 11A and 11B show structural examples of a monolithic activematrix circuit; and

[0058]FIGS. 12A through 12D show examples of equipment using a flatpanel display according to a tenth embodiment.

DESCRIPTION OF PREFERRED EMBODIMENTS

[0059] [First Embodiment]

[0060]FIGS. 1A through 1F are section views showing a fabricationprocess according to the present embodiment. In FIGS. 1A through 1F, alogic circuit 101 is formed on the left side of the paper and a matrixcircuit 102 on the right side. At first, a base film (not shown) ofsilicon oxide of 2000 Å in thickness is formed on a substrate (Corning7059) 11 by means of sputtering. Further, an intrinsic (I-type)amorphous silicon film of 500 to 1500 Å in thickness, or 500 Å forexample, is deposited by means of plasma CVD. Then, it is crystallizedby means of known thermal annealing. It may be crystallized by a methodof irradiating light energy beam such as laser light or a lamp, insteadof the thermal annealing, or by using combinations of the methods. Themethod of irradiating with a lamp is called a rapid thermal annealing(RTA) method.

[0061] The silicon film thus obtained is patterned by means ofphotolithography to separate into islands to form island regions 12 aand 12 b for TFTs of a logic circuit and an island region 12 c for a TFTof a matrix circuit.

[0062] Further, a silicon oxide film 13 of 1000 Å in thickness isdeposited as a first gate insulating layer by means of sputtering. Inthe sputtering, silicon oxide is used as a target, a substratetemperature during the sputtering is 200 to 400° C., or 350° C. forexample, and sputtering atmosphere composed of oxygen and argon is setto have a ratio of argon/oxygen=0 to 0.5, or 0.1 or less for example(FIG. 1A).

[0063] Further, a silicon nitride film of 1500 to 3000 Å in thickness isdeposited by means of plasma CVD. It is then etched except a portionnear a channel of the TFT of the matrix circuit to obtain a second gateinsulating layer 14 (FIG. 1B).

[0064] Following to that, a silicon film (containing 0.1 to 2% ofphosphorus) of 3000 to 8000 Å in thickness, or 6000 Å for example, isdeposited by means of low pressure CVD. Then, it is etched to form gateelectrodes 15 a, 15 b and 15 c (FIG. 1C).

[0065] The first gate insulating layer and the second gate insulatinglayer are then etched by using the respective gate electrodes as a maskto expose the surface of the island-like semiconductor regions. As aresult, gate insulating films comprising the first gate insulatinglayers 13 a and 13 b (both used for the logic circuit) and a gateinsulating film comprising the first gate insulating layer 13 c and thesecond gate insulating layer 14 c (used for the matrix circuit) areobtained (FIG. 1D).

[0066] Next, impurities (phosphorus and boron) are implanted to thesilicon region by using the gate electrodes as a mask by means of knownion doping. Phosphine (PH₃) and diborane (B₂H₆) are used as the dopinggas and the dosage thereof is 1×10¹⁵ to 8×10¹⁵ cm⁻², e.g. 2×10 ¹⁵ cm⁻²of phosphorus and 5×10¹⁵ cm⁻² of boron. As a result, a P-type impurityregion 16 a and N-type impurity regions 16 b and 16 c are formed.

[0067] After that, the impurities are activated by means of laserannealing. Although a KrF excimer laser (wavelength: 248 nm, pulsewidth: 20 nsec) is used as the laser, other lasers such as a XeF excimerlaser (wavelength: 353 nm), a XeCl excimer laser (wavelength: 308 nm),an ArF excimer laser (wavelength: 193 nm) and the like may be used.Energy density of the laser is 200 to 400 mJ/cm², or 250 mJ/cm² forexample, and the laser is irradiated by 2 to 10 shots, or 2 shots forexample, per one spot. The substrate is heated up to 100 to 450° C., or250° C. for example, in irradiating the laser. Further, this activationcan be also performed by the RTA method.

[0068] Thus the impurity regions 16 a through 16 c are activated. Thisstep may be carried out also by means of thermal annealing (FIG. 1E).Further, this activation can be also performed by the RTA method.

[0069] Following to that, a silicon oxide film 17 of 6000 Å in thicknessis formed as an interlayer insulator by means of plasma CVD. Contactholes are formed therethrough and electrode/wires 18 a and 18 b for thelogic circuit and an electrode/wire 18 c for the matrix circuit areformed by using metallic materials such as a multi-layered film oftitanium nitride and aluminum.

[0070] Further, an indium tin oxide film (ITO) of 500 to 1000 Å inthickness, or 800 Å for example, is formed by means of sputtering and ispatterned to form a pixel electrode 19.

[0071] Finally, annealing is implemented at 350° C. for 30 minuteswithin one atmospheric pressure of hydrogen atmosphere. Through theabove-mentioned steps, a semiconductor integrated circuit having aP-channel type TFT 20 a and an N-channel type TFT 20 b of the logiccircuit and a TFT 20 c of the matrix circuit is completed. It is notedthat a buffer transistor of a driver circuit may be fabricated in thesame manner with the transistor of the matrix circuit described in theabove-mentioned embodiment (FIG. 1F).

[0072] [Second Embodiment]

[0073]FIGS. 2A through 2F are section views showing a fabricationprocess according to the present embodiment. In FIGS. 2A through 2F, alogic circuit 201 is formed on the left side of the paper and a matrixcircuit 202 on the right side. At first, a base film (not shown) ofsilicon oxide of 2000 Å in thickness is formed on a substrate (Corning7059) 21. Further, an intrinsic (I-type) crystalline silicon film of 500to 1500 Å in thickness, or 500 Å for example, is deposited by means ofplasma CVD. The silicon film is then separated into islands to formisland regions 22 a and 22 b for TFTs of a logic circuit and an islandregion 22 c for a TFT of a matrix circuit.

[0074] Further, a silicon oxide film 23 of 1000 Å in thickness isdeposited as a first gate insulating layer by means of plasma CVD (FIG.2A).

[0075] Further, a silicon nitride film of 1000 Å in thickness isdeposited by means of plasma CVD. Then, the silicon nitride film isetched except a portion near a channel of the TFT of the matrix circuit.Here, the portion having a width of 5 μm from an edge of a gateelectrode to be formed later is left. Thus, a second gate insulatinglayer 24 is obtained (FIG. 2B).

[0076] Following to that, a silicon film (containing 0.1 to 2% ofphosphorus) of 3000 to 8000 Å in thickness, or 6000 Å for example, isdeposited by means of low pressure CVD. It is then etched to form gateelectrodes 25 a, 25 b and 25 c (FIG. 2C).

[0077] Next, impurities (phosphorus and boron) are implanted to thesilicon region by using the gate electrodes as a mask by means of knownion doping. Phosphine (PH₃) and diborane (B₂H₆) are used as the dopinggas. Because through doping, i.e. doping carried out transmittingthrough a gate insulating film, is implemented in the presentembodiment, acceleration voltage is increased more than that of thefirst embodiment.

[0078] Further, while the doping is implemented at higher accelerationvoltage at the portion below the gate insulating layer 24 because thegate insulating film is thick there as compared to other parts, thedosage is lowered by 1 to 2 digits.

[0079] As a result, an N-type low concentration impurity region 26 d isformed in addition to a P-type high concentration impurity region 26 aand N-type high concentration impurity regions 26 b and 26 c. Thetechnology for changing the concentration of impurity by utilizing adifference of thickness of gate insulating films has been disclosed insuch as Japanese Patent Laid Open Nos. Hei. 7-169974, Hei. 7-169975,Hei. 7-218932, the disclosures of which are herein incorporated byreference (FIG. 2D).

[0080] After activating the impurities, a silicon nitride film 27 of4000 Å in thickness is formed as a first interlayer insulator by meansof plasma CVD. Contact holes are formed therethrough and electrode/wires28 a and 28 b for the logic circuit and an electrode/wire 28 c for thematrix circuit are formed by using aluminum (FIG. 2E).

[0081] Further, an organic resin film 29 is formed as a secondinterlayer insulator. Then, after forming contact holes thereon, anindium tin oxide film (ITO) of 800 Å in thickness is formed by means ofsputtering and is patterned to form a pixel electrode 30.

[0082] Through the above-mentioned steps, a semiconductor integratedcircuit having a P-channel type TFT 31 a and an N-channel type TFT 31 bof the logic circuit and a TFT 31 c of the matrix circuit is completed(FIG. 2F).

[0083] [Third Embodiment]

[0084]FIGS. 3A through 3F are section views showing a fabricationprocess according to the present embodiment. In FIGS. 3A through 3F, alogic circuit 301 is formed on the left side of the paper and a matrixcircuit 302 on the right side. At first, an intrinsic (I-type)crystalline silicon film of 800 Å in thickness is formed on a substrate(quartz) 32. The silicon film is then separated into islands to formisland regions 33 a and 33 b for TFTs of a logic circuit and an islandregion 33 c for a TFT of a matrix circuit.

[0085] Further, a silicon oxide film 34 of 1000 Å in thickness isdeposited on the whole surface by means of plasma CVD (FIG. 3A).

[0086] Next, the silicon oxide film 34 at the part of the logic circuitis etched to form a first gate insulating layer 34 a in the matrixcircuit region (FIG. 3B).

[0087] Following to that, a gate insulating film of silicon oxide isformed on the surface of the silicon region by implementing thermaloxidation in 850 to 1150° C., or at 950° C. for example. At this time,the silicon oxide is formed so as to be 500 Å in thickness in the logiccircuit region thermally oxidized in the state in which the siliconlayer has been exposed. Because the surface of the matrix circuit iscovered by the silicon oxide film formed by means of the plasma CVD, theprogress of the thermal oxidation is more moderate and a thickness ofthe whole silicon oxide is 1500 Å or less. Thus, gate insulating films35 a, 35 b and 35 c are obtained (FIG. 3C).

[0088] Following to that, an aluminum film of 4000 to 6000 Å, or 5000 Åin thickness for example, is deposited by means of sputtering. It isthen etched to form gate electrodes 36 a, 36 b and 36 c. Further, thegate insulating films 35 a through 35 c are etched by using the gateelectrodes as a mask (FIG. 3D).

[0089] Next, impurities (phosphorus and boron) are implanted to thesilicon region by using the gate electrodes as a mask by means of knownion doping to form a P-type impurity region 37 a and N-type impurityregions 37 b and 37 c (FIG. 3E).

[0090] After activating the impurities, a silicon oxide film 38 of 4000Å in thickness is formed as an interlayer insulator. Contact holes areformed therethrough and electrode/wires 39 a and 39 b for the logiccircuit and an electrode/wire 39 c for the matrix circuit are formed byaluminum.

[0091] Through the above-mentioned steps, a semiconductor integratedcircuit having a P-channel type TFT 40 a and an N-channel type TFT 40 bof the logic circuit and a TFT 40 c of the matrix circuit is completed(FIG. 3F).

[0092] The pixel electrode may be added in the manner as described inthe second embodiment.

[0093] [Fourth Embodiment]

[0094]FIGS. 4A through 4F are section views showing a fabricationprocess according to the present embodiment. In FIGS. 4A through 4F, alogic circuit 401 is formed on the left side of the paper and a matrixcircuit 402 on the right side. At first, an intrinsic (I-type) crystalsilicon film of 600 Å in thickness is formed on a substrate (quartz) 41.The silicon film is then separated into islands to form island regions42 a and 42 b for TFTs of a logic circuit and an island region 42 c fora TFT of a matrix circuit.

[0095] Further, a silicon oxide film 43 of 1000 Å in thickness isdeposited on the whole surface by means of plasma CVD (FIG. 4A).

[0096] Next, the silicon oxide film 43 is etched except a portion near achannel of the TFT of the matrix circuit. Here, the portion having awidth of 3 μm from the edge of a gate electrode to be formed later isleft. Thus, a first gate insulating layer 43 a is formed in the matrixcircuit region (FIG. 4B).

[0097] Following to that, a gate insulating film of silicon oxide isformed on the surface of the silicon region by implementing thermaloxidation at 950° C. At this time, the silicon oxide is formed to be 400Å in thickness in the logic circuit region thermally oxidized in thestate in which the silicon layer has been exposed. Thus, gate insulatingfilms 44 a, 44 b and 44 c are obtained (FIG. 4C).

[0098] Following to that, an aluminum film of 4000 Å in thickness isdeposited by means of sputtering. It is then etched to form gateelectrodes 45 a, 45 b and 45 c (FIG. 4D).

[0099] Next, impurities (phosphorus and boron) are implanted to thesilicon region by using the gate electrodes as a mask by means of knownion doping. At this time, two-stage doping is implemented by changingacceleration voltage similarly to the second embodiment to form anN-type low concentration impurity region 46 d in addition to a P-typehigh concentration impurity region 46 a and N-type high concentrationimpurity regions 46 b and 46 c (FIG. 4E).

[0100] After activating the impurities, a silicon oxide film 47 of 6000Å in thickness is formed as an interlayer insulator. Contact holes areformed therethrough and electrode/wires 48 a and 48 b for the logiccircuit and an electrode/wire 48 c for the matrix circuit are formed byaluminum.

[0101] Through the above-mentioned steps, a semiconductor integratedcircuit having a P-channel type TFT 49 a and an N-channel type TFT 49 bof the logic circuit and a TFT 49 c of the matrix circuit is completed(FIG. 4F).

[0102] [Fifth Embodiment]

[0103]FIGS. 5A through 5F are section views showing a fabricationprocess according to the present embodiment. In FIGS. 5A through 5F, alogic circuit 501 is formed on the left side of the paper and a matrixcircuit 502 on the right side. At first, an intrinsic (I-type)crystalline silicon film of 600 Å in thickness is formed on a substrate(quartz) 51. The silicon film is then separated into islands to formisland regions 52 a and 52 b for TFTs of a logic circuit and an islandregion 52 c for a TFT of a matrix circuit.

[0104] Further, silicon oxide films 53 a, 53 b and 53 c of 500 Å inthickness are formed by means of thermal oxidation (FIG. 5A).

[0105] Next, the silicon oxide films 53 a and 53 b existing on the partof the logic circuit are etched (FIG. 5B).

[0106] The state shown in FIG. 5B obtained by the steps so far can beobtained also by forming a resist film 93 except the part of the logiccircuit after separating the silicon film into the islands (FIG. 9A), byimplementing the thermal oxidation (FIG. 9B) and then by removing theresist film (FIG. 9C).

[0107] Following to that, a gate insulating film of silicon oxide isformed on the surface of the silicon region by implementing anotherthermal oxidation at 950° C. At this time, the silicon oxide is formedto be 400 Å in thickness in the logic circuit region thermally oxidizedin the state in which the silicon layer has been exposed. Thus, gateinsulating films 54 a, 54 b and 54 c are obtained (FIG. 5C).

[0108] Following to that, an aluminum film of 4000 Å in thickness isdeposited by means of sputtering. It is then etched to form gateelectrodes 55 a, 55 b and 55 c. Further, the gate insulating films 54 a,54 b and 54 c are etched by using the gate electrodes as a mask (FIG.5D).

[0109] Next, impurities (phosphorus and boron) are implanted to thesilicon region by using the gate electrodes as a mask by means of knownion doping. Then, a P-type impurity region 56 a and N-type impurityregions 56 b and 56 c are formed (FIG. 5E).

[0110] After activating the impurities, a silicon oxide film 57 of 6000Å in thickness is formed as an interlayer insulator. Contact holes areformed therethrough and electrode/wires 58 a and 58 b for the logiccircuit and an electrode/wire 58 c for the matrix circuit are formed byaluminum.

[0111] Through the above-mentioned steps, a semiconductor integratedcircuit having a P-channel type TFT 59 a and an N-channel type TFT 59 bof the logic circuit and a TFT 59 c of the matrix circuit is completed(FIG. 5F).

[0112] [Sixth Embodiment]

[0113]FIGS. 6A through 6F are section views showing a fabricationprocess according to the present embodiment. In FIGS. 6A through 6F, alogic circuit 601 is formed on the left side of the paper and a matrixcircuit 602 on the right side. At first, an intrinsic (I-type)crystalline silicon film of 600 Å in thickness is formed on a substrate(quartz) 61. The silicon film is then separated into islands to formisland regions 62 a and 62 b for TFTs of a logic circuit and an islandregion 62 c for a TFT of a matrix circuit.

[0114] Further, silicon oxide films 63 a, 63 b and 63 c of 500 Å inthickness are formed by means of thermal oxidation (FIG. 6A).

[0115] Next, the silicon oxide films 63 a and 63 b existing on the partof the logic circuit are etched. The silicon oxide film 63 c at thematrix circuit is left (FIG. 6B).

[0116] Next, the silicon oxide films 63 a, 63 b and 63 c are etchedexcept the silicon oxide film 63 d at the part near the channel of theTFT of the matrix circuit. The silicon oxide film 63 d is left up to thepart having a width of 3 μm from the edge of a gate electrode to beformed later (FIG. 6B).

[0117] The state shown in FIG. 6B obtained by the steps so far can beobtained also by forming a resist film 103 except the part having thewidth of 3 μm from the edge of the gate electrode to be formed laterafter separating the silicon film into the islands (FIG. 10A), byimplementing the thermal oxidation (FIG. 10B) and then by removing theresist film (FIG. 10C).

[0118] Following to that, a gate insulating film of silicon oxide isformed on the surface of the silicon region by implementing anotherthermal oxidation at 950° C. At this time, the silicon oxide is formedto be 400 Å in thickness in the part where the silicon layer is exposed.Thus, gate insulating films 64 a, 64 b and 64 c are obtained (FIG. 6C).

[0119] Next, an aluminum film of 4000 Å in thickness is deposited bymeans of sputtering. It is then etched to form gate electrodes 65 a, 65b and 65 c (FIG. 6D).

[0120] Next, impurities (phosphorus and boron) are implanted to thesilicon region by using the gate electrodes as a mask by means of knownion doping. At this time, the two-stage doping is carried out bychanging acceleration voltage similarly to the second or fourthembodiment to form an N-type low concentration impurity region 66 d inaddition to a P-type high concentration impurity region 66 a and N-typehigh concentration impurity regions 66 b and 66 c (FIG. 6E).

[0121] After activating the impurities, a silicon oxide film 67 of 6000Å in thickness is formed as an interlayer insulator. Contact holes areformed therethrough and electrode/wires 68 a and 68 b for the logiccircuit and an electrode/wire 68 c for the matrix circuit are formed byaluminum.

[0122] Through the above-mentioned steps, a semiconductor integratedcircuit having a P-channel type TFT 69 a and an N-channel type TFT 69 bof the logic circuit and a TFT 69 c of the matrix circuit is completed(FIG. 6F).

[0123] [Seventh Embodiment]

[0124] While the case of thickening the gate insulating film of thematrix circuit has been shown in the third embodiment, a gate insulatingfilm of circuits in which priority is given to high operating speed suchas a shift register circuit, a CPU circuit, a decoder circuit, a memorycircuit and others among peripheral circuits is thinned as compared to agate insulating film of circuits in which priority is given to highwithstand voltage such as a high withstand voltage switching circuit anda buffer circuit in the present embodiment.

[0125] The gate insulating film of the circuit in which priority isgiven to high operating speed among the peripheral circuits is thinnedby using the same process with that in the third embodiment.

[0126] [Eighth Embodiment]

[0127] While the case of thinning the gate insulating film of thecircuit in which priority is given to high operating speed has beenshown in the seventh embodiment, a length of the channel is shortenedfurther by reducing a width of a gate electrode of the circuit havingthe thin gate insulating film in the present embodiment.

[0128] The present embodiment shares the same process with the thirdembodiment up to the step of depositing the aluminum film of 4000 to6000 Å, or 5000 Å in thickness for example, by means of sputtering afterforming the silicon oxide film.

[0129] In the present embodiment, with respect to the peripheralcircuits 700, a width of gate electrodes 76 a and 76 b of the circuit701 in which priority is given to high operating speed, for example, ashift register circuit, is reduced to 1 μm which is narrower than awidth of a gate electrode 76 c (width: 2 μm) of the circuit 702 in whichpriority is given to high withstand voltage, for example, a buffercircuit, in an etching step thereafter (FIG. 7A).

[0130] Here, although the ratio of the width of the gate electrode ofthe circuit in which priority is given to high operating speed to thewidth of the gate electrode of the circuit in which priority is given tohigh withstand voltage has been 0.5 in the present embodiment, it is notlimited to the value of the present embodiment so long as it is within arange of 0.1 to 0.5.

[0131] Next, impurities (phosphorus and boron) are implanted to thesilicon region by using the gate electrodes as a mask by means of knownion doping to form a P-type impurity region 77 a and N-type impurityregions 77 b and 77 c (FIG. 7B).

[0132] Through this step, the length of the channel of the circuit inwhich priority is given to high operating speed is reduced to 80% orless of the length of the channel of the circuit in which priority isgiven to high withstand voltage.

[0133] Further, a length of the channel formed in contact with the gateelectrode formed in this step has almost the same length with the widthof the gate electrode.

[0134] Accordingly, the ratio of the length of the channel of thecircuit in which priority is given to high operating speed to that ofthe circuit in which priority is given to high withstand voltage becomes0.5 similarly to the ratio of the width of the gate electrodes in thepresent embodiment. The ratio of the length of the channels is not alsolimited to the value of the present embodiment so long as it is withinthe range of 0.1 to 0.5, similarly to the width of the gate electrodes.

[0135] After activating the impurities, a silicon oxide film 78 of 4000Å in thickness is formed as an interlayer insulator. Contact holes areformed therethrough and electrode/wires 79 a and 79 b for the circuit inwhich priority is given to high operating speed and an electrode/wire 79c for the circuit in which priority is given to high withstand voltageare formed by aluminum.

[0136] Through the above-mentioned steps, a semiconductor integratedcircuit having a P-channel type TFT 80 a and an N-channel type TFT 80 bof the circuit in which priority is given to high operating speed and aTFT 80 c of the circuit in which priority is given to high withstandvoltage is completed (FIG. 7C).

[0137] The pixel electrode may be added in the manner as described inthe second embodiment.

[0138] [Ninth Embodiment]

[0139] While the case of laminating the first and second gate insulatingfilms in the matrix circuit has been shown in the first embodiment, alength of the channel is shortened by reducing the width of the gateelectrode of the circuit in which only the first gate insulating film isused in the present embodiment.

[0140] The present embodiment shares the same process with the firstembodiment up to the step of depositing the silicon film (containing 0.1to 2% of phosphorus) of 3000 to 8000 Å, or 6000 Å in thickness forexample, on the gate insulating film by means of the low pressure CVD.

[0141] In the present embodiment, with respect to the peripheralcircuits 800, a width of gate electrodes 86 a and 86 b of the circuit801 in which priority is given to high operating speed, for example, ashift register circuit, is reduced to 1 μm which is narrower than awidth of a gate electrode 86 c (width: 2 μm) of the circuit 802 in whichpriority is given to high withstand voltage, for example, a buffercircuit, in an etching step thereafter (FIG. 8A).

[0142] Here, although the ratio of the width of the gate electrode ofthe circuit in which priority is given to high operating speed to thewidth of the gate electrode of the circuit in which priority is given tohigh withstand voltage has been 0.5 in the present embodiment, it is notlimited to the value of the present embodiment so long as it is within arange of 0.1 to 0.5.

[0143] The first gate insulating layer and the second gate insulatinglayer are etched by using respective gate electrodes as a mask to exposethe surface of the island semiconductor regions (FIG. 8A).

[0144] Next, impurities (phosphorus and boron) are implanted to thesilicon region by using the gate electrodes as a mask by means of knownion doping. Phosphine (PH₃) and diborane (B₂H₆) are used as the dopinggas and the dosage thereof is 1×10¹⁵ to 8×10¹⁵ cm⁻², e.g. 2×10 ¹⁵ cm⁻²of phosphorus and 5×10¹⁵ cm⁻² of boron. As a result, a P-type impurityregion 87 a and N-type impurity regions 87 b and 87 c are formed (FIG.8B).

[0145] After activating the impurities, a silicon oxide film 88 of 4000Å in thickness is formed as an interlayer insulator. Contact holes areformed therethrough and electrode/wires 89 a and 89 b for the circuit inwhich priority is given to high operating speed and an electrode/wire 89c for the circuit in which priority is given to high withstand voltageare formed by aluminum.

[0146] Through the above-mentioned steps, the semiconductor integratedcircuit having a P-channel type TFT 90 a and an N-channel type TFT 90 bof the circuit in which priority is given to high operating speed and aTFT 90 c of the circuit in which priority is given to high withstandvoltage is completed (FIG. 8C).

[0147] Further, a length of the channel formed in contact with the gateelectrode formed in this step has substantially the same width with thatof the gate electrode. Accordingly, the ratio of the length of thechannel of the circuit in which priority is given to high operatingspeed to that of the circuit in which priority is given to highwithstand voltage is not also limited to the value of the presentembodiment so long as it is within the range of 0.1 to 0.5, similarly tothe width of the gate electrode of the present invention.

[0148] The pixel electrode may be added in the manner as described inthe second embodiment.

[0149] [Tenth Embodiment]

[0150] A liquid crystal display fabricated by utilizing the presentspecification is called as a flat panel type display device. As suchdisplay device, there have been known ones using EL(electroluminescence) materials and using EC (electrochromic) materials,beside one utilizing the optical characteristics of liquid crystal. Theinvention disclosed in the present specification may be utilized in anactive matrix type flat panel display which uses those materials and inwhich peripheral driving circuits and the like are integrated. Theliquid crystal display (LCD) device manufactured using the presentinvention can be applied to either a transmission type or a reflectiontype.

[0151] Such display may be utilized in the following uses. FIG. 12Ashows an equipment called a digital still camera, an electronic cameraor a video movie which can display motion pictures.

[0152] This equipment has functions of electronically keeping imagestaken by a CCD camera (or other adequate photographic means) disposed ata camera section 2002 and of displaying the images on a display device2003 disposed within a main body 2001. The equipment may be manipulatedby control buttons 2004.

[0153] The invention disclosed in the present specification may beutilized in the display device constructed as described above. Becausepower consumption may be saved by utilizing the invention disclosed inthe present specification, it is useful for the portable equipment asshown in FIG. 12A which is supposed to be driven by a battery.

[0154]FIG. 12B shows a portable personal computer. This equipment isprovided with a display device 2104 on an openable cover 2102 attachedto a main body 2101 and allows to input various information from a keyboard 2103 and to run various operations.

[0155] It is also useful to utilize the invention disclosed in thepresent specification for the display device 2104 arranged as shown inFIG. 12B.

[0156]FIG. 12C shows a case when the flat panel display is utilized in acar navigation system. The car navigation system comprises an antennasection 2304 and a main body provided with a display 2302.

[0157] Switching of various information required in navigation is can bemade by control buttons 2303. It is generally controlled by a remotecontrol unit not shown.

[0158]FIG. 12D shows a case of a projection type liquid crystal display.In the figure, light emitted from a light source 2402 is opticallymodulated by a liquid crystal display device 2403 and is turned into animage. The image is reflected by mirrors 2404 and 2405 to be projectedon a screen 2406.

[0159] As shown in the above-mentioned embodiments, the presentinvention allows the TFT which can operate at high speed in low voltageand the TFT which is characterized by the high withstand voltage to beformed on one and the same substrate. Applying this to the liquidcrystal display allows the reliability, the power consumption and thecharacteristics to be improved as a whole.

[0160] It is noted that the features and advantages of the presentinvention may be clearly understood if one notices on that theconventional semiconductor integrated circuit technology has notrequired to change the thickness of the gate insulating film activelylike the present invention. In the conventional semiconductor integratedcircuit (in digital circuits in particular), voltage to be used has beenall the same within the circuit. For instance, the memory area and theperipheral circuit have been driven by single voltage in a DRAM.

[0161] However, a liquid crystal display requires a plurality ofvoltages because voltage suitable for the liquid crystal materialdiffers from voltage suitable for driving transistors in the liquidcrystal display. Generally, the former is higher than the latter.

[0162] If there is a plurality of voltages, dimensions of a transistorssuited to that also have to be changed. The present invention hasnoticed on this point. Accordingly, the idea of the present inventionwould not be brought out from the technology of the conventionalsemiconductor integrated circuit driven by single voltage. Thus, thepresent invention is useful from the industrial point of view.

What is claimed is:
 1. A semiconductor integrated circuit comprising: afirst thin film transistor formed on a substrate, said first thin filmtransistor having a first gate insulating film and a first gateelectrode; and a second thin film transistor formed on said substrate,said second thin film transistor having a second gate insulating filmand a second gate electrode, wherein a variation of a first voltageapplied to said first gate electrode is smaller than a variation of asecond voltage applied to a second gate electrode, and wherein athickness of said first gate insulating film is 80% or less of athickness of said second gate insulating film.
 2. A semiconductorintegrated circuit comprising: a first thin film transistor formed on asubstrate, said first thin film transistor having a first gateinsulating film and a first gate electrode; and a second thin filmtransistor formed on said substrate, said second thin film transistorhaving a second gate insulating film and a second gate electrode,wherein a variation of a first voltage applied to said first gateelectrode is smaller than a variation of a second voltage applied to asecond gate electrode, and wherein at least one layer of anotherinsulating layer is used for said second gate insulating film inaddition to an insulating layer composing said first gate insulatingfilm.
 3. A semiconductor integrated circuit comprising: a first thinfilm transistor formed on a substrate, said first thin film transistorhaving a first gate insulating film and a first gate electrode; and asecond thin film transistor formed on said substrate, said second thinfilm transistor having a second gate insulating film and a second gateelectrode, wherein said second gate insulating film includes a firstinsulating layer and a second insulating layer, wherein a variation of afirst voltage applied to said first gate electrode is smaller than avariation of a second voltage applied to a second gate electrode,wherein said first insulating layer is said first gate insulating filmand said second insulating layer is formed by a different process fromsaid first insulating layer.
 4. A semiconductor integrated circuitcomprising: a first thin film transistor formed on a substrate, saidfirst thin film transistor having a first gate insulating film and afirst channel region; and a second thin film transistor formed on saidsubstrate, said second thin film transistor having a second gateinsulating film and a second channel region, wherein a first thicknessof said first gate insulating film is 80% or less of a second thicknessof said second gate insulating film, and wherein a first length of saidfirst channel region is 80% or less of a second length of said secondchannel region.
 5. A circuit according to claims 1 wherein said firstthin film transistor composes a logic circuit and said second thin filmtransistor composes a matrix circuit.
 6. A circuit according to claims 1wherein said first thin film transistor composes a logic circuit andsaid second thin film transistor composes a high withstand voltageswitching circuit.
 7. A circuit according to claims 1 wherein said firstthin film transistor composes a logic circuit and said second thin filmtransistor composes a buffer circuit.
 8. A circuit according to claims 1wherein said second thin film transistor comprises at least a lowconcentration impurity region formed by utilizing a difference of thethickness of the gate insulating films.
 9. A circuit according to claim3 wherein said first insulating layer has a different chemical componentfrom said second insulating layer.
 10. A circuit according to claim 3wherein either one of said first insulating layer or said secondinsulating layer is formed by thermal oxidation.
 11. A method forfabricating a semiconductor integrated circuit, said method comprisingthe steps of: forming a first thin film semiconductor region for a firstthin film transistor and a second thin film semiconductor region for asecond thin film transistor; forming a first insulating layer coveringboth of said first and second thin film semiconductor regions;selectively removing said first insulating layer to remove all of saidfirst insulating layer covering at least said second thin filmsemiconductor region; and forming a second insulating layer coveringboth of said first and second thin film semiconductor regions.
 12. Amethod for fabricating a semiconductor integrated circuit, said methodcomprising the steps of: forming a first thin film semiconductor regionfor a first thin film transistor and a second thin film semiconductorregion for a second thin film transistor; forming a first insulatinglayer covering both of said first and second thin film semiconductorregions; forming a second insulating layer covering said firstinsulating layer; and selectively removing said second insulating layerto remove all of said second insulating layer covering at least saidsecond thin film semiconductor region.
 13. A method for fabricating asemiconductor integrated circuit, said method comprising the steps of:forming a first thin film semiconductor region for a first thin filmtransistor and a second thin film semiconductor region for a second thinfilm transistor; selectively forming a first insulating layer coveringboth of said first and second thin film semiconductor regions except aportion of at least said second thin film semiconductor region; andforming a second insulating layer covering both of said first and secondthin film semiconductor regions.
 14. A method according to claims 11wherein said first insulating layer is formed by thermal oxidation. 15.A method according to claims 11 wherein said second thin film transistorcomposes a logic circuit and said first thin film transistor composes amatrix circuit.
 16. A method according to claims 11 wherein said secondthin film transistor composes a logic circuit and said first thin filmtransistor composes a high withstand voltage switching circuit.
 17. Amethod according to claims 11 wherein said second thin film transistorcomposes a logic circuit and said first thin film transistor composes abuffer circuit.
 18. A method according to claims 11 further comprisingthe steps of: forming a first gate electrode and a second gateelectrode, said first gate electrode having a different width from saidsecond gate electrode, forming a source region, a drain region andchannels by doping, said channels having different lengths.
 19. Acircuit according to claims 2 wherein said first thin film transistorcomposes a logic circuit and said second thin film transistor composes amatrix circuit.
 20. A circuit according to claims 3 wherein said firstthin film transistor composes a logic circuit and said second thin filmtransistor composes a matrix circuit.
 21. A circuit according to claims4 wherein said first thin film transistor composes a logic circuit andsaid second thin film transistor composes a matrix circuit.
 22. Acircuit according to claims 2 wherein said first thin film transistorcomposes a logic circuit and said second thin film transistor composes ahigh withstand voltage switching circuit.
 23. A circuit according toclaims 3 wherein said first thin film transistor composes a logiccircuit and said second thin film transistor composes a high withstandvoltage switching circuit.
 24. A circuit according to claims 4 whereinsaid first thin film transistor composes a logic circuit and said secondthin film transistor composes a high withstand voltage switchingcircuit.
 25. A circuit according to claims 2 wherein said first thinfilm transistor composes a logic circuit and said second thin filmtransistor composes a buffer circuit.
 26. A circuit according to claims3 wherein said first thin film transistor composes a logic circuit andsaid second thin film transistor composes a buffer circuit.
 27. Acircuit according to claims 4 wherein said first thin film transistorcomposes a logic circuit and said second thin film transistor composes abuffer circuit.
 28. A circuit according to claims 2 wherein said secondthin film transistor comprises at least a low concentration impurityregion formed by utilizing a difference of the thickness of the gateinsulating films.
 29. A circuit according to claims 3 wherein saidsecond thin film transistor comprises at least a low concentrationimpurity region formed by utilizing a difference of the thickness of thegate insulating films.
 30. A circuit according to claims 4 wherein saidsecond thin film transistor comprises at least a low concentrationimpurity region formed by utilizing a difference of the thickness of thegate insulating films.
 31. A method according to claims 12 wherein saidsecond thin film transistor composes a logic circuit and said first thinfilm transistor composes a matrix circuit.
 32. A method according toclaims 13 wherein said second thin film transistor composes a logiccircuit and said first thin film transistor composes a matrix circuit.33. A method according to claims 12 wherein said second thin filmtransistor composes a logic circuit and said first thin film transistorcomposes a high withstand voltage switching circuit.
 34. A methodaccording to claims 13 wherein said second thin film transistor composesa logic circuit and said first thin film transistor composes a highwithstand voltage switching circuit.
 35. A method according to claims 12wherein said second thin film transistor composes a logic circuit andsaid first thin film transistor composes a buffer circuit.
 36. A methodaccording to claims 13 wherein said second thin film transistor composesa logic circuit and said first thin film transistor composes a buffercircuit.
 37. A method according to claims 12 further comprising thesteps of: forming a first gate electrode and a second gate electrode,said first gate electrode having a different width from said second gateelectrode, forming a source region, a drain region and channels bydoping, said channels having different lengths.
 38. A method accordingto claims 13 further comprising the steps of: forming a first gateelectrode and a second gate electrode, said first gate electrode havinga different width from said second gate electrode, forming a sourceregion, a drain region and channels by doping, said channels havingdifferent lengths.
 39. A device according to claim 1 wherein said firstthin film transistor composes a first circuit for high operating speedand said second thin film transistor composes a second circuit for highwithstand voltage.